Description of Work on Fault Coverage of ATPG schemes and Design for Testability in VLSI Circuits

I have worked on modeling the delay faults and providing guidance to the ATPG schemes for delay fault testing. Delay faults alter the timing characteristics of a circuit but do not change the logical behavior. For example, a two input XNOR gate outpts a logic '1' when its both inputs are equal but its output may become valid after the clock pulse triggered a memory element to accept the output thus invalidating the stored result. The extra delay in the output was not part of the design and it resulted due to the alteration of RC values in the signal path. The RC values may have been affected by global or local manufacturing defects. I designed a software tool IDFA (Inductive Delay Fault Analyzer) that accepts a VLSI layout file and produces the frequency distribution and sizes of the delay faults that may result due to localized spot defects. The probability of occurrence of delay faults is dependent on the physical layout of the circuit. IDFA uses the layout in predicting the delay faults thus its results are more reliable than the traditional delay fault models based on logical gates and paths.

Currently I have the following project available in this field:

* Implementing a delay fault guidance scheme in Java or C++ that uses the results of IDFA and a hybrid model to provide test guidance for ATPG schemes